1. Field of Invention
The present invention is related to nonvolatile memories and configurable logic elements and in particular, to a configurable logic elements, which is implemented by trapped-charge nonvolatile memory.
2. Description of Related Art
Programmable logic arrays such as program logic arrays (PLA) and field programmable gate arrays (FPGA) comprise configurable logic elements and configurable interconnection paths. Different functions may be implemented upon the same hardware chip by programming the configuration elements, which are conventionally static random access memory (SRAM) or latches connected to pass gates. FIG. 1 shows a programmable logical connection of prior art, in which the pass transistor 11 is connected between two logic areas 13 and 14. The gate of the pass transistor 11 is connected to a latch 12. The setting of the latch 12 controls whether or not the pass transistor 11 will be turned on or off. Generally, a latch and/or an SRAM is used to control the state of the pass transistor because the process technology can be simple CMOS. U.S. Pat. No. 4,750,155 (Hsieh) is directed to a five-transistor memory cell which includes two inverters and a pass transistor that can be reliably read and written. However, the disadvantages of using latches and SRAM is that the programmable elements are volatile, which means that the state of the latch and the SRAM must be re-established each time power is turned on.
Non-volatile memory can also be incorporated into the programming configuration elements in the form of fuses or anti-fuses, as well as erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM) cells. Fuse-based non-volatile memory (NVM) involves separating segments of wiring paths with a high concentrated current; and are therefore, not re-programmable. U.S. Pat. No. 4,899,205 (Handy, et al.) is directed to an electrically-programmable low-impedance anti-fuse element. However, EPROM and EEPROM devices can be repeatedly programmed, but require high voltages for program and erase. Thicker oxide devices as well as more complex processes are required, which can degrade the chip performance and increase the processing cost.
In general, in an FPGA there are several types and variations of logical connections. In FIG. 1, two logic areas 13 and 14 are connected together via a NMOS pass gate 11. Using a single gate provide the best utilization of semiconductor area, but the transmitted signal between the two logic areas is degraded by the VT (threshold voltage) of the transistor 11. In order to avoid the VT drop, it is also possible to form the connection using a NMOS-PMOS complementary pass-gate, or with a thicker-oxide NMOS transistor and a boosted gate voltage. An FPGA implemented with reprogrammable non-volatile memory incorporated within a logical connection has been implemented by a floating gate type of memory. In U.S. Pat. No. 5,576,568 (Kowshik) a single-transistor electrically alterable switch is directed to a floating gate memory, which is programmed and erased by Fowler-Nordheim tunneling.
In U.S. Pat. No. 6,252,273 B1 (Salter III et al.) a nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase is directed to a device configuration in which two floating gate devices share a single floating gate; one device functions as the memory storage device and the other device functions as the logic switch cell. Shown in the prior art of FIG. 2, the source and drain of the logic switch cell 17 is connected to a logical array, whereas the source and drain of the memory storage 18 can be biased to program and erase electrons to and from the common floating gate. Programming and erasing the switch transistor 17 is effected entirely by the tunneling in the electron tunneling device 19. The two main advantages of this device is smaller area than a typical SRAM device, and non-volatility. Thus, the logic array containing the device of FIG. 2 is already configured upon boot-up; however, having a floating gate device in the path of logic could have a negative impact on speed, because a thicker oxide device is slower. One way to reduce the speed disadvantage is to lower the threshold voltage of the floating gate logic switch 17 until it becomes a negative value, thus increasing the current drive of the device.
U.S. Pat. No. 5,587,603 (Kowshik) is directed towards a zero power non-volatile latch consisting of a PMOS floating gate transistor and an NMOS floating gate transistor, with both devices sharing the same floating gate and control gates. Shown in FIG. 3, the drains of the devices are also connected together to form the output terminal, which is generally applied to the gate of the logic switch gate. Storage of electrons in the common floating gate will determine whether the logic switch gate is on or off.
U.S. Pat. No. 5,587,603 (Kowshik) a two-transistor zero-power electrically-alterable non-volatile latch is directed to a latch consisting of a PMOS floating gate transistor 22 and an NMOS floating gate transistor 23 where both devices share the same floating gate 24 and control gates as shown in FIG. 3. The drains of the transistors are also connected together to form the output terminal 25, which is generally applied to the gate of the logic switch gate. Storage of electrons in the common floating gate determines whether the logic switch gate is on or off.
The preceding and other prior art, such as NVM in programmable logic, have been implemented with floating gate types of flash memory. However there has been a recent trend to use charge trap mediums instead of floating gate to store charge. In embedded CMOS applications like NVM programmable logic, trap-charge memories provide better reliability, good scalability, simple processing and in some cases, lower voltage operation.
Four basic types of trap-based memory cells are shown in FIGS. 4a, 4b, 4c and 4d. FIG. 4a shows a basic planar structure in which nitride or some other trap material 401 is placed under the control gate MGATE. Here charge is stored uniformly throughout the trap film 401. Electrons are injected and ejected by tunneling through the channel. Voltage conditions for program and erase are given in TABLE 1a. If the tunneling mechanism utilized is direct tunneling, the bottom oxide thickness should be thin, on the order of approximately twenty Angstroms. If the tunneling mechanism used is Fowler-Nordheim, then the bottom oxide thickness can be thicker than approximately 40 Angstroms, but higher voltages may be needed. Several types of band gap engineered oxides are currently being investigated in the industry, which may reduce the voltage requirement during Fowler-Nordheim tunneling.